In the manufacture of microelectronic devices, packaging density is becoming increasingly important. Stacking of the dice of a multi-processor microelectronic device is one way to improve the packaging density of a microelectronic device. Stacked microelectronic devices are typically formed by stacking two or more wafers with integrated circuitry formed thereon, forming bonded wafers, and then dicing the stacked wafers into individual stacked devices. FIG. 5 illustrates a stacked microelectronic device 236, which may result from the fabrication technique briefly described above. Device 236 comprises a first microelectronic die 216 having an active surface 218, and an integrated circuitry layer 222, which contains integrated circuitry not shown in detail. Typically, the integrated circuitry layer is formed to a depth of approximately 10 microns. An interconnect layer 224 is formed on the die 216, and is illustrated as a plurality of interconnect structures, but may additionally comprise multiple layers of conductive traces separated by dielectric material (not shown). The interconnect layer 224 provides routes for electrical communication between integrated circuits, integrated circuit components, and external devices, for example.
Device 236 comprises a second microelectronic die 202, which additionally contains an integrated circuitry layer 208 and an interconnect layer 212. The physical attachment of interconnect layer 224 to interconnect layer 212 may electrically interconnect integrated circuitry layer 222 with integrated circuitry layer 208. Die 202 may be thinned, prior to dicing, and a plurality of conductive vias 228 may be formed on the back surface 226 to be in electrical contact with the integrated circuitry layer 208. A plurality of solder balls 232 may be formed such that one or more solder balls are in electrical contact with one or more vias. Formation of the plurality of vias 228 and plurality of solder balls 232 may make it possible to route input/output signals, power, and ground to and from the integrated circuitry layers, for example.
Typically, thinning of one of the stacked wafers is performed by use of one or more mechanical and/or chemical processes, such as a polishing process, for example. These processes may cause mechanical stresses in the unsupported portions of the wafer being thinned. Unsupported portions of the wafer may include, for example, the areas of the wafer not supported by interconnect structures, for example. These mechanical stresses may result in undesirable effects such as chipping, cracking, or other mechanical damage, which may result in the wafer and/or individual stacked devices being unusable. A need, therefore, exists for a method of forming stacked devices that reduces or eliminates these undesirable effects.